I. Field of Invention
The present invention relates generally to interface circuits, and more particularly in one embodiment to a data output stage that is integrated into a memory chip.
II. Prior Art
FIG. 1 illustrates a prior art output stage implemented using CMOS technology. A NAND gate 3 has a first input for receiving an output enable (OE) signal and a second input for receiving a true (IN) signal. The NAND gate 3 generates a logical low when the OE signal is asserted high and IN is asserted high. A NAND gate 5 has a first input for receiving the output enable (OE) signal and a second input for receiving a complement signal ( IN). The differential inputs (the IN and the IN signals) are generated by a functional circuit (e.g., the bitlines from a memory). The NAND gate 5 generates the inverted logical state of the IN signal when the OE signal is asserted (e.g., when the IN signal is asserted, the output of NAND gate 5 is a logical low).
A first inverter 7 and a second inverter 9 are coupled to the NAND gate 3 and the NAND gate 5, respectively. Each of the inverters has inputs to receive power signals (i.e., V.sub.cc and V.sub.ss (e.g., ground)). These inverters 7 and 9 invert the output of the NAND gate 3 and the NAND gate 5 and also provide gain for the signal passing through the inverters.
A first NMOS transistor 11 and a second NMOS transistor 13 are coupled to the first inverter 7 and the second inverter 9, respectively. The NMOS transistors 11 and 13 are coupled to each other in series to form an output stage for generating V.sub.out. The first NMOS transistor 11 is known in the art as a "pull-up" transistor for bringing V.sub.out to the power rail (V.sub.cc) minus one threshold voltage (V.sub.TH). Similarly, the NMOS transistor 13 is known in the art as a "pull-down" transistor for pulling V.sub.out to V.sub.ss (e.g., ground).
FIG. 2 illustrates the transistor implementation of the first and second inverters 7 and 9. As is well known in the art, an inverter may be implemented using a PMOS transistor 15 coupled in series to an NMOS transistor 17 with the gates of the NMOS and the PMOS transistors coupled together. The first and second inverters 7 and 9 comprise the gain stage of this circuit.
In an alternative prior art approach, a pass transistor is employed to clamp the output voltage. This pass transistor in effect clamps the output high voltage (V.sub.OH) to approximately one threshold voltage (V.sub.TH) below the power supply voltage (V.sub.cc) (i.e., V.sub.OH equals V.sub.cc minus V.sub.TH).
As computer components and systems transition to lower voltages (e.g., 5 V to 3.3 V), there is a need for interface circuitry to interface a component operating with the 5 volt power supply to a circuit component operating with a 3.3 V voltage supply.
The prior art interface circuits have the following disadvantages. First, these prior art interface circuits are susceptible to process temperature and voltage variations. In other words, the performance of the interface circuit varies widely and depends upon the type of process used to manufacture the component, and the temperature and voltage at which the component is operating. Accordingly, when a system designer is incorporating the interface circuit into his design, he cannot be assured of meeting voltage specifications because of the widely divergent and varying results that stem from process differences, temperature and voltage range discrepancies.
For example, a change of one volt in the power supply voltage generally corresponds to a one volt change on the output of the interface circuit. When designing in a computer system having all components operating with a 5 V power supply, this performance dependency on power supply voltage fluctuations is not as significant as in a lower power system because the V.sub.OH(max) (the maximum output high voltage) necessary for the proper operation of all the circuits is not specified for in a 5 V power supply system. However, when the receiving component has a 3.3 V power supply, the V.sub.OH (max) (voltage output high) is specified. Accordingly, a signal provided to a 3.3 V circuit component must meet more stringent voltage requirements than a signal provided to a 5 V computer part.
Accordingly, it is evident that it would be desirable to have an interface data output clamp for interfacing a 5 V component to a 3.3 V component. Moreover, it would be desirable that the performance of this data output stage is not as sensitive to fluctuations in the power supply voltage as prior art data outputs.